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[VHDL-FPGA-Verilog] dp

Description: datapath code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[VHDL-FPGA-Verilog] InstMemory

Description: instruction memory code in verilog for pipeline processor
Platform: | Size: 1024 | Author: kallu | Hits:

[VHDL-FPGA-Verilog] 4add

Description: verilog 实现两级流水线加法器 源代码 以及测试代码 adder16_2.v test_adder16_2.v-verilog Implement two pipeline adder source code and test code adder16_2.v test_adder16_2.v
Platform: | Size: 1024 | Author: keyCSky | Hits:

[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 用verilog实现的一个基于流水线结构的正余弦信号发生器，六级流水线-Verilog realize a pipeline structure of the sine and cosine signal generator , six pipeline
Platform: | Size: 1024 | Author: 郭良谦 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU2

Description: Modulsim下Verilog写的五级流水线32位简易CPU-five level pipeline CPU written in Verilog.
Platform: | Size: 772096 | Author: tiancai | Hits:

[VHDL-FPGA-Verilog] My_RASrm

Description: 流水线处理器的Verilog代码，结构简单，基本功能-the pipeline processor，code in Verilog
Platform: | Size: 103424 | Author: wineer | Hits:

[VHDL-FPGA-Verilog] Homework4

Description: 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
Platform: | Size: 2210816 | Author: liu | Hits:

[Windows Develop] cordic

Description: verilog实现的cordic算法，经典的流水线实现的cordic平方根的算法-cordic algorithm verilog implementation of the the classic pipeline implemented cordic square root algorithm
Platform: | Size: 1024 | Author: 刘大远 | Hits:

[VHDL-FPGA-Verilog] src

Description: 自己写的一个求两个32位操作数的最大公约数处理器的verilog代码，采用的是流水线结构-A seek the greatest common divisor of two 32-bit operands processor verilog code pipeline structure
Platform: | Size: 4096 | Author: ray | Hits:

[Software Engineering] CHU92A

Description: MIPS pipeline datapath Figure 6.30 in Paterson and Hennessy s textbook [4]. The model will be ... Listing 1.1: Verilog code for the multiplexer. A00000AA
Platform: | Size: 351232 | Author: he | Hits:

[VHDL-FPGA-Verilog] s_mips

Description: FPGA verilog mips processor - pipeline reference
Platform: | Size: 2048 | Author: howyaaa | Hits:

[VHDL-FPGA-Verilog] pipline

Description: 用verilog实现的流水线cpu,实现高效率的CPU基本运算-Pipeline cpu with verilog
Platform: | Size: 932864 | Author: 郭昕昳 | Hits:

[VHDL-FPGA-Verilog] adder16_2

Description: １６位２级流水线加法器的ｖｅｒｉｌｏｇ设计-16 2 pipeline adder Verilog design
Platform: | Size: 1024 | Author: 张山 | Hits:

[VHDL-FPGA-Verilog] 5-17

Description: 用verilog实现一个基于流水线结构的正、余弦信号发生器-Based on Pipeline Structure verilog to achieve a sine and cosine signal generator
Platform: | Size: 1024 | Author: 张山 | Hits:

[VHDL-FPGA-Verilog] adder8_4

Description: 用Verilog HDL编写的8位加法器程序，加法器采用4级流水线的方式实现。-8-bit adder program written using Verilog HDL, the adder 4 pipeline.
Platform: | Size: 95232 | Author: 李桐 | Hits:

[ARM-PowerPC-ColdFire-MIPS] PipelineCPU

Description: 这是我们设计的一个MIPS流水线CPU，基于Verilog HDL语言实现。它与传统的MIPS流水线CPU不同点在于，5个流水段各自维护一个变量(SelType)表明当前正在执行的指令类型，这样处理数据冒险、loaduse冒险或者跳转冒险时候每个段都能知道其他段正在处理的语句，从而方便我们的处理。-This is a MIPS pipelined CPU based on Verilog HDL language to achieve. It the the MIPS pipelined CPU differences that each of the five pipeline stages maintenance a variable (SelType) indicates that the currently executing instruction types, this treatment data Adventure loaduse adventure or jump adventure when each segment can know The statement is being processed, in order to facilitate our processing.
Platform: | Size: 11357184 | Author: 武翔宇 | Hits:

[VHDL-FPGA-Verilog] booth-16_16-multiplier

Description: 由verilog编写的利用booth编码的16*16有符号乘法器的代码，没有pipeline-a 16*16 multiplier with booth coding by verilog
Platform: | Size: 11264 | Author: pyc | Hits:

[Other] proc_pipe

Description: A 5 stage pipeline CPU written in verilog codes
Platform: | Size: 35840 | Author: gnuhcyee | Hits:

[VHDL-FPGA-Verilog] arbiter2

Description: The logic design of an efficient and fast round robin arbiter in Verilog or any other HDL language relies on the capability to find the next requestor to grant without losing cycles and with minimal logical stages. Using the fastest logic constructs like Parallel Prefix Computation (PPC) and the most suitable architecture will result in a fast and efficient arbiter suitable for pipeline integration of a multiple queue structure
Platform: | Size: 1024 | Author: thanh | Hits:
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